Building the TD4 4-Bit CPU: A Deep Dive

Forget abstract simulations; you want to feel how a CPU works. You’ve seen countless videos of complex 8-bit machines, but what if you crave a deeper, more fundamental understanding? You’re not alone. The problem is that most modern processors are black boxes. To truly grasp the essence of computation, you need to strip it down to its barest, most fundamental components.

This is where the TD4 4-bit CPU shines. It’s not about building a practical device; it’s about building a foundational understanding of how a Central Processing Unit is architected using readily available, classic 74-series TTL logic ICs. The TD4 is the digital equivalent of learning to walk before you can run. It deliberately sacrifices practicality for pedagogical purity, forcing you to confront the raw mechanics of instruction fetching, decoding, and execution.

The TD4’s architecture is a masterclass in minimalism. At its core, it’s a hard-wired logic machine. You’ll be assembling it using components like the 74HC161 for registers and program counter, the 74HC153 multiplexers for data selection, and the 74HC283 as a 4-bit Arithmetic Logic Unit (ALU). The heart of its program storage, in its most common form, is a 16-byte ROM, often implemented with DIP switches acting as a diode matrix. This forces you to think about program memory at the most granular level.

The instruction set is deliberately tiny, typically comprising 12-14 commands for basic data movement, addition, I/O, and control flow (jumps). For instance, a Verilog implementation might look something like this within the core logic:

// Simplified snippet representing instruction decoding logic
wire [3:0] opcode;
// ... other logic ...

// Fetching instruction from ROM based on PC
assign opcode = rom_output[instruction_address_select];

// Example: Data Movement Instruction (e.g., LDA - Load Accumulator)
always @(posedge clk) begin
  if (instruction_decoder(opcode) == LDA_INSTRUCTION) begin
    accumulator <= rom_output[data_address_select]; // Load data from ROM
  end
end

// Example: Addition Instruction (e.g., ADD)
always @(posedge clk) begin
  if (instruction_decoder(opcode) == ADD_INSTRUCTION) begin
    accumulator <= accumulator + rom_output[data_address_select]; // Add data from ROM
  end
end

This is raw computation. You’re not dealing with high-level abstractions; you’re directly wiring logic gates to perform operations on 4-bit values (0-15). For those who prefer simulation and development, open-source resources like BG5DIW’s GitHub provide the necessary Verilog files (TD4.v, TD4_test.v) and even an assembler utility for creating programs. KiCad can be used to manage the PCB designs.

The TD4 sits within a broader ecosystem of educational hardware projects. Alternatives like Ben Eater’s 8-bit computer or the Nand2Tetris course offer similar deep dives, but the TD4’s 4-bit nature and TTL focus provide a uniquely accessible entry point. Its community, though niche, is active, with contributors exploring extensions like adding RAM or expanding the instruction set. However, it’s crucial to understand the TD4’s limitations. It’s not meant for practical tasks. Its 16-byte ROM and rudimentary instruction set mean you’ll be wrestling with single-digit arithmetic. Forget complex software; this is about understanding the fundamental cycles of a CPU.

If your goal is to learn the absolute bedrock of computer architecture, the TD4 is an unparalleled tool. It forces a hands-on engagement with logic gates, registers, and the instruction cycle that no microcontroller or simulator can replicate. It’s time-consuming, especially with the soldering involved for diode-matrix ROMs, but the reward is an intimate, visceral understanding of computation that is both rare and invaluable. If you need to run an application, grab a Raspberry Pi. If you want to understand how that application could run, build a TD4.